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| 1 ? fn6373.6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006-2008, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6236 high-efficiency, quad-output, main power supply controllers for notebook computers the isl6236 dual step-down, switch-mode power-supply (smps) controller generates logic-supply voltages in battery-powered systems. the isl6236 include two pulse-width modulation (pwm) controllers, 5v/3.3v and 1.5v/1.05v. the output of smps1 can also be adjusted from 0.7v to 5.5v. the smps2 output can be adjusted from 0v to 2.5v by setting refin2 voltage. an optional external charge pump can be monitored through se cfb. this device features a linear regulator providing 3.3v/5v, or adjustable from 0.7v to 4.5v output via ldorefin. the linear regulator provides up to 100ma output current with automatic linear-regulator bootstrapping to the byp input. when in switchover, the ldo output can source up to 200ma. the isl6236 includes on-board power-up sequencing, the power-good (pok) outputs, digital soft-start, and internal soft-stop output discharge that prevents negative voltages on shutdown. a constant on-time pwm control scheme operates without sense resistors and provi des 100ns response to load transients while maintaining a relatively constant switching frequency. the unique ultrasonic pulse-skipping mode maintains the switching frequency above 25khz, which eliminates noise in audio appl ications. other features include pulse skipping, which maximizes efficiency in light-load applications, and fixed-frequency pwm mode, which reduces rf interference in sensitive applications. features ? wide input voltage range 5.5v to 25v ? dual fixed 1.05v/3.3v and 1.5v/5.0v outputs or adjustable 0.7v to 5.5v (smps1) and 0v to 2.5v (smps2), 1.5% accuracy ? secondary feedback input (maintains charge pump voltage) ? 1.7ms digital soft-start and independent shutdown ? fixed 3.3v/5.0v, or adjustable output 0.7v to 4.5v, 1.5% (ldo): 200ma ? 3.3v reference voltage 2.0%: 5ma ? 2.0v reference voltage 1.0%: 50a ? constant on-time control with 100ns load-step response ? frequency selectable ?r ds(on) current sensing ? programmable current limit with foldback capability ? selectable pwm, skip or ultrasonic mode ? boot voltage monitor with automatic refresh ? independent pok1 and pok2 comparators ? soft-start with pre-biased output and soft-stop ? independent enable ? high efficiency - up to 97% ? very high light load efficiency (skip mode) ? 5mw quiescent power dissipation ? thermal shutdown ? extremely low component count ? pb-free (rohs compliant) applications ? notebook and sub-notebook computers ? pdas and mobile communication devices ? 3-cell and 4-cell li+ battery-powered devices ? ddr1, ddr2 and ddr3 power supplies ? graphic cards ? game consoles ? telecommunications ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6236irza isl6236 irz -40 to +100 32 ld 5x5 qfn l32.5x5b ISL6236IRZA-T* isl6236 irz -40 to +100 32 ld 5x5 qfn (tape and reel) l32.5x5b *please refer to tb347 for detai ls on reel specifications. notes: 1. these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb- free requirements of ipc/jedec j std-020. 2. for moisture sensitivity level (msl), please see device information page for isl6236 . for more information on msl please see techbrief tb363 . data sheet april 29, 2010
2 fn6373.6 april 29, 2010 pinout isl6236 (32 ld 5x5 qfn) top view refin2 ilim2 out2 skip pok2 en2 ugate2 phase2 byp out1 fb1 ilim1 pok1 en1 ugate1 phase1 ref ton vcc en ldo vref3 vin ldo ldorefin boot2 lgate2 pgnd gnd secfb pvcc lgate1 boot1 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10111213141516 isl6236 3 fn6373.6 april 29, 2010 absolute voltage ratings vin, en ldo to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +27v boot to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vcc, en, skip , ton, pvcc, pok to gnd . . . . . . . . . -0.3v to +6v ldo, fb1, refin2, ldorefin to gnd . . . -0.3v to (vcc + 0.3v) out, secfb, vref3, ref to gnd . . . . . . . . -0.3v to (vcc + 0.3v ugate to phase . . . . . . . . . . . . . . . . . . . . -0.3v to (pvcc + 0.3v) ilim to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vcc + 0.3v) lgate, byp to gnd . . . . . . . . . . . . . . . . . . -0.3v to (pvcc + 0.3v) pgnd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v ldo, ref, vref3 short circuit to gnd . . . . . . . . . . . . continuous vcc short circuit to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s ldo current (internal regulator) continuous . . . . . . . . . . . . 100ma ldo current (switched over to out1) continuous . . . . . . +200ma thermal information thermal resistance (typical) ja (c/w) jc (cw) 32 ld qfn (notes 3, 4) . . . . . . . . . . . . 32 3.0 operating temperature range . . . . . . . . . . . . . . . .-40c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter conditions min (note 6) typ max (note 6) units main smps controllers v in input voltage range ldo in regulation 5.5 25 v v in = ldo, vout1 <4.43v 4.5 5.5 v 3.3v output voltage in fixed mode v in = 5.5v to 25v, refin2 > (vcc - 1v), skip = 5v 3.285 3.330 3.375 v 1.05v output voltage in fixed mode v in = 5.5v to 25v, 3.0 < refin2 < (vcc - 1.1v), skip = 5v 1.038 1.05 1.062 v 1.5v output voltage in fixed mode v in = 5.5v to 25v, fb1 = vcc, skip = 5v 1.482 1.500 1.518 v 5v output voltage in fixed mode v in = 5.5v to 25v, fb1 = gnd, skip = 5v 4.975 5.050 5.125 v fb1 in output adjustable mode (note 7) v in = 5.5v to 25v 0.693 0.700 0.707 v refin2 in output adjustable mode v in = 5.5v to 25v 0.7 2.50 v secfb voltage v in = 5.5v to 25v 1.920 2.00 2.080 v smps1 output voltage adjust range smps1 0.70 5.50 v smps2 output voltage adjust range smps2 0.50 2.50 v smps2 output voltage accuracy (referred for refin2) refin2 = 0.7v to 2.5v, skip = vcc -1.0 1.0 % dc load regulation either smps, skip = vcc, 0a to 5a -0.1 % either smps, skip = ref, 0a to 5a -1.7 % either smps, skip = gnd, 0a to 5a -1.5 % line regulation either smps, 6v < v in < 24v 0.005 %/v current-limit current source temperature = +25c 4.75 5 5.25 a ilim adjustment range 0.2 2 v current-limit threshold (positive, default) ilim = vcc, gnd - phase (no temperature compensation) 93 100 107 mv isl6236 4 fn6373.6 april 29, 2010 current-limit threshold (positive, adjustable) gnd - phase v ilim = 0.5v 40 50 60 mv v ilim = 1v 93 100 107 mv v ilim = 2v 185 200 215 mv zero-current threshold skip = gnd, ref, or open, gnd - phase 3 mv current-limit threshold (negative, default) skip = vcc, gnd - phase -120 mv soft-start ramp time zero to full limit 1.7 ms operating frequency (v ton = gnd), skip = vcc smps 1 400 khz smps 2 500 khz (v ton = ref or open), skip = vcc smps 1 400 khz smps 2 300 khz (v ton = vcc), skip = vcc smps 1 200 khz smps 2 300 khz on-time pulse width v ton = gnd (400khz/500khz) v out1 = 5.00v 0.895 1.052 1.209 s v out2 = 3.33v 0.475 0.555 0.635 s v ton = ref or open (400khz/300khz) v out1 = 5.05v 0.895 1.052 1.209 s v out2 = 3.33v 0.833 0.925 1.017 s v ton = vcc (200khz/300khz) v out1 = 5.05v 1.895 2.105 2.315 s v out2 = 3.33v 0.833 0.925 1.017 s minimum off-time t a = -40c to +100c 200 300 425 ns t a = -40c to +85c 200 300 410 ns maximum duty cycle v ton = gnd v out1 = 5.05v 88 % v out2 = 3.33v 85 % v ton = ref or open v out1 = 5.05v 88 % v out2 = 3.33v 91 % v ton = vcc v out1 = 5.05v 94 % v out2 = 3.33v 91 % ultrasonic skip operating frequency skip = ref or open 25 37 khz internal regulator and reference ldo output voltage byp = gnd, 5.5v < v in < 25v, ldorefin < 0.3v, 0 < ildo < 100ma 4.925 5.000 5.075 v ldo output voltage byp = gnd, 5.5v < v in < 25v, ldorefin > (vcc -1v), 0 < ildo < 100ma 3.250 3.300 3.350 v ldo output in adjustable mode v in = 5.5v to 25v, v ldo = 2 x v ldorefin 0.7 4.5 v ldo output accuracy in adjustable mode v in = 5.5v to 25v, v ldorefin = 0.35v to 0.5v 2.5 % v in = 5.5v to 25v, v ldorefin = 0.5v to 2.25v 1.5 % ldorefin input range v ldo = 2 x v ldorefin 0.35 2.25 v ldo output current byp = gnd, v in = 5.5v to 25v (note 5) 100 ma ldo output current during switchover byp = 5v, v in = 5.5v to 25v, ldorefin < 0.3v 200 ma ldo output current during switchover to 3.3v byp = 3.3v, v in = 5.5v to 25v, ldorefin > (vcc - 1v) 100 ma ldo short-circuit current ldo = gnd, byp = gnd 200 400 ma electrical specifications no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 6) typ max (note 6) units isl6236 5 fn6373.6 april 29, 2010 undervoltage-lockout fault threshold rising edge of pvcc 4.35 4.5 v falling edge of pvcc 3.9 4.05 ldo 5v bootstrap switch threshold to byp rising edge at byp regulation point ldorefin = gnd 4.53 4.68 4.83 v ldo 3.3v bootstrap switch threshold to byp rising edge at byp regulation point ldorefin = vcc 3.0 3.1 3.2 v ldo 5v bootstrap switch equivalent resistance ldo to byp, byp = 5v, ldorefin > (vcc -1v) (note 5) 0.7 1.5 ldo 3.3v bootstrap switch equivalent resistance ldo to byp, byp = 3.3v, ldorefin < 0.3v (note 5) 1.5 3.0 vref3 output voltage no external load, vcc > 4.5v 3.235 3.300 3.365 v no external load, vcc < 4.0v 3.220 3.300 3.380 v vref3 load regulation 0 < i load < 5ma 10 mv vref3 current limit vref3 = gnd 10 17 ma ref output voltage no external load 1.980 2.000 2.020 v ref load regulation 0 < i load < 50a 10 mv ref sink current ref in regulation 10 a vin operating supply current both smpss on, fb1 = skip = gnd, refin2 = vcc v out1 = byp = 5.3v, v out2 = 3.5v 25 50 a vin standby supply current v in = 5.5v to 25v, both smpss off, en ldo = vcc 180 250 a vin shutdown supply current v in = 4.5v to 25v, en1 = en2 = en ldo = 0v 20 30 a quiescent power consumption both smpss on, fb1 = skip = gnd, refin2 = vcc, v out1 = byp = 5.3v, v out2 = 3.5v 57mw fault detection overvoltage trip threshold fb1 with respect to nominal regulation point +8 +11 +14 % refin2 with respect to nomi nal regulation point +12 +16 +20 % overvoltage fault propagation delay fb1 or refin2 delay with 50mv overdrive 10 s pok threshold fb1 or refin2 with respect to nominal output, falling edge, typical hysteresis = 1% -12-9-6% pok propagation delay falling edge, 50mv overdrive 10 s pok output low voltage i sink = 4ma 0.2 v pok leakage current high state, forced to 5.5v 1 a thermal-shutdown threshold +150 c out-of-bound threshold fb1 or refin2 wi th respect to nominal output voltage 5 % output undervoltage shutdown threshold fb1 or refin2 with respect to nominal output voltage 65 70 75 % output undervoltage shutdown blanking time from en signal 10 20 30 ms inputs and outputs fb1 input voltage low level 0.3 v high level vcc - 1.0 v refin2 input voltage out2 dynamic range, v out2 = v refin2 0.5 2.50 v fixed out2 = 1.05v 3.0 vcc - 1.1 v fixed out2 = 3.3v vcc - 1.0 v electrical specifications no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 6) typ max (note 6) units isl6236 6 fn6373.6 april 29, 2010 ldorefin input voltage fixed ldo = 5v 0.30 v ldo dynamic range, v ldo = 2 x v ldorefin 0.35 2.25 v fixed ldo = 3.3v vcc - 1.0 v skip input voltage low level (skip) 0.8 v float level (ultrasonic skip) 1.7 2.3 v high level (pwm) 2.4 v ton input voltage low level 0.8 v float level 1.7 2.3 v high level 2.4 v en1, en2 input voltage clear fault level/smps off level 0.8 v delay start level 1.7 2.3 v smps on level 2.4 v en ldo input voltage rising edge 1.2 1.6 2.0 v falling edge 0.94 1.00 1.06 v input leakage current v ton = 0v or 5v -1 +1 a v en = v en ldo = 0v or 5v -0.1 +0.1 a vskip = 0v or 5v -1 +1 a v fb1 = vsecfb = 0v or 5v -0.2 +0.2 a v refin = 0v or 2.5v -0.2 +0.2 a v ldorefin = 0v or 2.75v -0.2 +0.2 a internal boot diode v d forward voltage pvcc - v boot , i f = 10ma 0.65 0.8 v i boot leakage leakage current v boot = 30v, phase = 25v, pvcc = 5v 500 na mosfet drivers ugate gate-driver sink/source current ugate1, ugate2 forced to 2v 2 a lgate gate-driver source current lgate1 (source), lgate2 (source), forced to 2v 1.7 a lgate gate-driver sink current lgate1 (sink), lgate2 (sink), forced to 2v 3.3 a ugate gate-driver on-resistance bst - phase forced to 5v (note 5) 1.5 4.0 lgate gate-driver on-resistance lgate, high state (pull-up) (note 5) 2.2 5.0 lgate, low state (pull-down) (note 5) 0.6 1.5 dead time lgate rising 15 20 35 ns ugate rising 20 30 50 ns out1, out2 discharge on-resistance 25 40 notes: 5. limits established by characte rization and are not production tested. 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise s pecified. temperature limits established by characterization and are not production tested. 7. does not apply in pfm mode (see further details on page 26). electrical specifications no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, vbyp = 5v, pvcc = 5v, ven_ldo = 5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 6) typ max (note 6) units isl6236 7 fn6373.6 april 29, 2010 pin descriptions pin number name function 1 ref 2v reference output. bypass to gnd with a 0.1f (min) capacitor. ref can source up to 50a for external loads. loading ref degrades fb and output accuracy according to the ref load-regulation error. 2 ton frequency select input. connect to gnd for 400khz/500 khz operation. connect to ref (or leave open) for 400khz/300khz operation. connect to vcc for 200khz/3 00khz operation (5v/3.3v smps switching frequencies, respectively.) 3 vcc analog supply voltage input for pwm core. bypass to gnd with a 1f ceramic capacitor. 4 en ldo ldo enable input. the ldo is enabled if en ldo is within logic high level and disabled if en ldo is less than the logic low level. 5 vref3 3.3v reference output. vref3 can source up to 5ma for external loads. bypass to gnd with a 0.01f capacitor if loaded. leave open if there is no load. 6 vin power-supply input. vin is used for the constant-on-time pw m on-time one-shot circuits. vin is also used to power the linear regulators. the linear regulators are powered by smps1 if out1 is set greater than 4.78v and byp is tied to out1. connect vin to the battery input and bypass with a 1f capacitor. 7 ldo linear-regulator output. ldo can provide a total of 100ma external loads. the ldo regulate at 5v if ldorefin is connected to gnd. when the ldo is set at 5v and byp is within 5v switchover threshold, the internal regulator shuts down and the ldo output pin connects to byp through a 0.7 switch. the ldo regulate at 3.3v if ldorefin is connected to vcc. when the ldo is set at 3.3v and byp is wi thin 3.3v switchover threshold, the internal regulator shuts down and the ldo output pin connects to byp through a 1.5 switch. bypass ldo output with a minimum of 4.7f ceramic. 8 ldorefin ldo reference input. connect ldorefin to gnd for fix ed 5v operation. connect ldorefin to vcc for fixed 3.3v operation. ldorefin can be used to program ldo output voltage from 0.7v to 4.5v. ldo output is two times the voltage of ldorefin. there is no switchover in adjustable mode. 9 byp byp is the switchover source voltage for the ldo when ldor efin connected to gnd or vcc. connect byp to 5v if ldorefin is tied to gnd. connect byp to 3.3v if ldorefin is tied to vcc. 10 out1 smps1 output voltage-sense input. connect to the smps1 output. out1 is an input to the constant on-time-pwm on-time one-shot circuit. it also serves as the smps1 feedback input in fixed-voltage mode. 11 fb1 smps1 feedback input. connect fb1 to gnd for fixed 5v operation. connect fb1 to vcc for fixed 1.5v operation connect fb1 to a resistive voltage-divider from out1 to gnd to adjust the output from 0.7v to 5.5v. 12 ilim1 smps1 current-limit adjustment. the gnd-phase1 current -limit threshold is 1/10th the voltage seen at ilim1 over a 0.2v to 2v range. there is an internal 5a current source from vcc to ilim1. connect ilim1 to ref for a fixed 200mv threshold. the logic current limit threshold is default to 100mv value if ilim1 is higher than vcc - 1v. 13 pok1 smps1 power-good open-drain output. pok1 is low when the smps1 output voltage is more than 10% below the normal regulation point or during soft-start. pok1 is high im pedance when the output is in regulation and the soft-start circuit has terminated. po k1 is low in shutdown. 14 en1 smps1 enable input. the smps1 is enabled if en1 is great er than the logic high level and disabled if en1 is less than the logic low level. if en1 is connected to ref, the smps1 st arts after the smps2 reaches regulation (delay start). drive en1 below 0.8v to clear fault level and reset the fault latches. 15 ugate1 high-side mosfet floating gate-driver output for smps1. ugate1 swings between phase1 and boot1. 16 phase1 inductor connection for smps1. phase1 is the internal lower supply rail for the ugate1 high-side gate driver. phase1 is the current-sense input for the smps1. 17 boot1 boost flying capacitor connec tion for smps1. connect to an external capa citor according to the typical application circuits (figures 66, 67 and 68). see ?mosfe t gate drivers (ugate, lgate)? on page 27. 18 lgate1 smps1 synchronous-rectifi er gate-drive output. lgate1 swings between gnd and pvcc. 19 pvcc pvcc is the supply voltage for the low-side mosfet driver lgate. connect a 5v power source to the pvcc pin and bypass with a 1f mlcc ceramic capacitor. refer to figure 69 - a switch connects pvcc to vcc with 10 when in normal operation and is disconnected when in shutdown mode. an external 10 resistor from pvcc to vcc is prohibited as it will create a leakage path from vin to gnd in shutdown mode. 20 secfb the secfb is used to monitor the optional external 14v charge pump. connect a resistiv e voltage-divider from 14v charge pump output to gnd to detect the output. if secfb drops below the threshold voltage, lgate1 turns on for 300ns. this will refresh the external charge pump driven by lgate1 without over-discharging the output voltage. isl6236 8 fn6373.6 april 29, 2010 21 gnd analog ground for both smps and ldo. connect exter nally to the underside of the exposed pad. 22 pgnd power ground for smps controller. connect pgnd externally to the underside of the exposed pad. 23 lgate2 smps2 synchronous-rectifi er gate-drive output. lgate2 swings between gnd and pvcc. 24 boot2 boost flying capacitor connec tion for smps2. connect to an external capa citor according to the typical application circuits (figures 66, 67 and 68). see ?mosfe t gate drivers (ugate, lgate)? on page 27 . 25 phase2 inductor connection for smps2. phase2 is the internal lower supply rail for the ugate2 high-side gate driver. phase2 is the current-sense input for the smps2. 26 ugate2 high-side mosfet floating gate-driver output for smps2. ugate1 swings between phase2 and boot2. 27 en2 smps2 enable input. the smps2 is enabled if en2 is great er than the logic high level and disabled if en2 is less than the logic low level. if en2 is connected to ref, the smps2 st arts after the smps1 reaches regulation (delay start). drive en2 below 0.8v to clear fault level and reset the fault latches. 28 pok2 smp2 power-good open-drain output. pok2 is low w hen the smps2 output voltage is more than 10% below the normal regulation point or during soft-start. pok2 is high im pedance when the output is in regulation and the soft-start circuit has terminated. po k2 is low in shutdown. 29 skip low-noise mode control. connect skip to gnd for normal idle-mode (pulse-skipping) operation or to vcc for pwm mode (fixed frequency). connect to ref or leav e floating for ultrasonic skip mode operation. 30 out2 smps2 output voltage-sense input. connect to the smps2 output. out2 is an input to the constant on-time-pwm on-time one-shot circuit. it also serves as the smps2 feedback input in fixed-voltage mode. 31 ilim2 smps2 current-limit adjustment. the gnd-phase1 current -limit threshold is 1/10th the voltage seen at ilim2 over a 0.2v to 2v range. there is an internal 5a current source from vcc to ilim2. connect ilim2 to ref for a fixed 200mv. the logic current limit threshold is default to 100mv value if ilim2 is higher than vcc - 1v. 32 refin2 output voltage control for smps2. connect refin2 to vcc for fixed 3.3v. connect refin2 to vref3 for fixed 1.05v. refin2 can be used to program smps2 output voltage from 0.5v to 2.50v. smps2 output voltage is 0v if refin2 <0.5v. pin descriptions (continued) pin number name function typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. figure 1. v out2 = 1.05v efficiency vs load (300khz) figure 2. v out1 = 1.5v efficiency vs load (200khz) 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 output load (a) efficiency (%) 1.000 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 10.000 0 10 20 30 40 50 60 70 80 90 100 0.010 0.100 1.000 10.00 0 output load (a) efficiency (%) 0.001 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode isl6236 9 fn6373.6 april 29, 2010 figure 3. v out2 = 3.3v efficiency vs load (500khz) figure 4. v out1 = 5v efficiency vs load (400khz) figure 5. v out2 = 1.05v regulation vs load (300khz) figure 6. v out1 = 1.5v regulation vs load (200khz) figure 7. v out2 = 3.3v regulation vs load (500khz) figure 8. v out1 = 5v regulation vs load (400khz) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 10.000 output load (a) efficiency (%) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 10.000 output load (a) efficiency (%) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 1.050 1.052 1.054 1.056 1.058 1.060 1.062 1.064 1.066 1.068 1.070 0.001 0.010 0.100 1.000 10.000 output load (a) output voltage (v) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 1.500 1.505 1.510 1.520 1.525 1.530 1.535 1.540 0.001 0.010 0.100 1.000 output load (a) output voltage (v) 10.000 1.515 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 0.001 0.010 0.100 1.000 10.000 output load (a) output voltage (v) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 5.00 5.02 5.04 5.06 5.08 5.10 5.12 5.14 5.16 0.001 0.010 0.100 1.000 10.000 output load (a) output voltage (v) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode isl6236 10 fn6373.6 april 29, 2010 figure 9. v out2 = 1.05v power dissipation vs load (300khz) figure 10. v out1 = 1.5v power dissipation vs load (200khz) figure 11. v out2 = 3.3v power dissipation vs load (500khz) figure 12. v out1 = 5v power dissipation vs load (400khz) figure 13. v out2 = 1.05v output voltage regulation vs v in (pwm mode) figure 14. v out2 = 1.05v output voltage regulation vs v in (skip mode) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 0.0 0.5 1.0 1.5 2.0 2.5 0.001 0.010 0.100 1.000 10.000 output load (a) power dissipation (w) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 0.0 0.5 1.0 1.5 2.0 2.5 0.001 0.010 0.100 1.000 10.000 output load (a) power dissipation (w) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.001 0.010 0.100 1.000 10.000 output load (a) power dissipation (w) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.001 0.010 0.100 1.000 10.000 output load (a) power dissipation (w) 7v in skip mode 7v in pwm mode 7v in ultra skip mode 12v in skip mode 12v in pwm mode 25v in skip mode 25v in pwm mode 25v in ultra skip mode 12v in ultra skip mode 1.048 1.050 1.052 1.054 1.056 1.058 1.060 1.062 1.064 5 7 9 1113151719212325 input voltage (v) output voltage (v) mid load pwm max load pwm no load pwm 1.048 1.050 1.052 1.054 1.056 1.058 1.060 1.062 1.064 1.066 1.068 5 7 9 1113151719212325 input voltage (v) output voltage (v) no load pwm mid load pwm max load pwm isl6236 11 fn6373.6 april 29, 2010 figure 15. v out1 = 1.5v output voltage regulation vs v in (pwm mode) figure 16. v out1 = 1.5v output voltage regulation vs v in (skip mode) figure 17. v out2 = 3.3v output voltage regulation vs v in (pwm mode) figure 18. v out2 = 3.3v output voltage regulation vs v in (skip mode) figure 19. v out1 = 5v output voltage regulation vs v in (pwm mode) figure 20. v out1 = 5v output voltage regulation vs v in (skip mode) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 1.504 1.506 1.508 1.510 1.512 1.514 1.516 1.518 output voltage (v) 5 7 9 1113151719212325 input voltage (v) no load pwm max load pwm mid load pwm 1.500 1.505 1.510 1.515 1.520 1.525 1.530 5 7 9 11 13 15 17 19 21 23 25 input voltage (v) output voltage (v) mid load pwm no load pwm max load pwm 3.310 3.315 3.320 3.325 3.330 3.335 3.340 7 9 11 13 15 17 19 21 23 25 input voltage (v) output voltage (v) no load pwm max load pwm mid load pwm 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 7 9 11 13 15 17 19 21 23 25 input voltage (v) output voltage (v) no load pwm max load pwm mid load pwm 5.040 5.045 5.050 5.055 5.060 5.065 7 9 11 13 15 17 19 21 23 25 input voltage (v) output voltage (v) no load pwm max load pwm mid load pwm 5.02 5.04 5.06 5.08 5.10 5.12 5.14 7 9 11 13 15 17 19 21 23 25 input voltage (v) output voltage (v) max load pwm mid load pwm no load pwm isl6236 12 fn6373.6 april 29, 2010 figure 21. v out2 = 1.05v frequency vs load figure 22. v out2 = 1.05v ripple vs load figure 23. v out1 = 1.5v frequency vs load figure 24. v out1 = 1.5v ripple vs load figure 25. v out2 = 3.3v frequency vs load figure 26. v out2 = 3.3v ripple vs load typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 0 50 100 150 200 250 300 0.001 0.010 0.100 1.000 10.00 0 output load (a) frequency (khz) pwm ultra-skip skip 0 5 10 15 20 25 30 35 40 45 50 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm ultra-skip skip 0 50 100 150 200 250 0.001 0.010 0.100 1.000 10.000 output load (a) frequency (khz) pwm ultra-skip skip 0 5 10 15 20 25 30 35 40 45 50 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm ultra-skip skip 0 100 200 300 400 500 600 0.001 0.010 0.100 1.000 10.000 output load (a) frequency (khz) pwm ultra-skip skip 0 2 4 6 8 10 12 14 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm skip ultra-skip isl6236 13 fn6373.6 april 29, 2010 figure 27. v out1 = 5v frequency vs load figure 28. v out1 = 5v ripple vs load figure 29. ldo output 5v vs load figure 30. ldo output 3.3v vs load figure 31. v ref3 vs load figure 32. charge pump vs load (pwm) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 0 50 100 150 200 250 300 350 400 450 0.001 1.000 output load (a) frequency (khz) 10.000 skip ultra-skip pwm 0 5 10 15 20 25 30 35 40 0.001 0.010 0.100 1.000 10.000 output load (a) ripple (mv) pwm skip ultra-skip 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 0 50 100 150 200 output load (ma) output voltage (v) byp = 0v byp = 5v 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 0 50 100 150 200 output load (ma) output voltage (v) byp = 3.3v byp = 0v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0610 output load (ma) output voltage (v) 24 8 12.5 13.0 13.5 14.0 14.5 15.0 15.5 010 output load (ma) output voltage (v) 2458 isl6236 14 fn6373.6 april 29, 2010 figure 33. pwm no load input current vs v in (en = en2 = en ldo = vcc) figure 34. skip no load input current vs v in (en1 = en2 = en ldo = vcc) figure 35. standby input current vs v in (en = en2 = 0, en ldo = vcc) figure 36. shutdown input current vs v in (en = en2 = en ldo = 0) figure 37. ref, vref3, ldo = 5v, cp, no load figure 38. start-up v out1 = 5v (no load, skip mode) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) 20 25 30 35 40 45 50 7 9 11 13 15 17 19 21 23 25 input voltage (v) input current (ma) 0.0 200 400 800 1400 7 9 11 13 15 17 19 21 23 25 input voltage (v) input current (a) 600 1000 1200 173.0 173.5 174.5 175.0 175.5 176.0 176.5 177.0 177.5 7 9 11 13 15 17 19 21 23 25 input voltage (v) input current (a) 174.0 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 7 9 11 13 15 17 19 21 23 25 input voltage (v) input current (a) ref 1v/div v ref3 500mv/div ldo 1v/div cp 5v/div en1 5v/div v out1 2v/div il1 2a/div pok1 2v/div isl6236 15 fn6373.6 april 29, 2010 figure 39. start-up v out1 = 5v (no load, pwm mode) figure 40. start-up v out1 = 5v (full load, pwm mode) figure 41. start-up v out2 = 3.3v (no load, skip mode) figure 42. start-up v out1 = 3.3v (no load, pwm mode) figure 43. start-up v out1 = 3.3v (full load, pwm mode) figure 44. delayed start-up (v out1 =5v, v out2 =3.3v, en1 = ref) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) v out1 2v/div il1 2a/div pok1 2v/div en1 5v/div en1 5v/div v out1 2v/div il1 5a/div pok1 2v/div en2 5v/div v out2 2v/div pok2 2v/div il2 2a/div en2 5v/div v out2 2v/div pok2 2v/div il2 2a/div en2 5v/div v out2 2v/div il2 5a/div pok2 2v/div en2 5v/div v out2 2v/div v out1 2v/div pok1 5v/div pok2 5v/div isl6236 16 fn6373.6 april 29, 2010 figure 45. delayed start-up (v out1 =5v, v out2 =3.3v, en2 = ref) figure 46. shutdown (v out1 =5v, v out2 =3.3v, en2 = ref) figure 47. load transient v out1 = 5v figure 48. load transient v out1 = 5v (skip) figure 49. load transient v out1 = 3.3v (pwm) figure 50. load transient v out1 = 3.3v (skip) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) en1 5v/div v out2 2v/div vout1 2v/div pok2 5v/div pok1 5v/div pok1 or pok2 5v/div v out1 2v/div v out2 2v/div en1 5v/div lgate1 5v/div v out1 ripple 50mv/div il1 5a/div v out2 ripple 50mv/div lgate1 5v/div v out1 ripple 100mv/div il1 5a/div v out2 ripple 50mv/div lgate1 5v/div v out1 ripple 20mv/div il2 5a/div v out2 ripple 50mv/div lgate2 5v/div v out1 ripple 20mv/div il2 5a/div v out2 ripple 50mv/div isl6236 17 fn6373.6 april 29, 2010 figure 51. v out2 tracking to refin2 figure 52. ldo tracking to ldorefin figure 53. start-up v out1 = 1.5v (no load, skip mode) figure 54. start-up v out1 = 1.5v (no load, pwm mode) figure 55. start-up v out1 = 1.5v (full load, pwm mode) figure 56. start-up v out2 = 1.05v (no load, skip mode) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) refin2 0.5v/div ldo ripple 50mv/div v out ripple 20mv/div v out2 0.5v/div ldorefin 0.5v/div ldo 1v/div v out ripple 20mv/div v out2 ripple 50mv/div en1 5v/div v out1 0.5v/div il1 2a/div pok1 2v/div en1 5v/div v out1 0.5v/div il1 2a/div pok1 2v/div en1 5v/div v out1 0.5v/div il1 5a/div pok1 2v/div en2 5v/div v out2 0.5v/div il2 2a/div pok2 2v/div isl6236 18 fn6373.6 april 29, 2010 figure 57. start-up v out1 = 1.05v (no load, pwm mode) figure 58. start-up v out1 = 1.05v (full load, pwm mode) figure 59. delayed start-up (v out1 =1.5v, v out2 = 1.05v, en1 = ref) figure 60. delayed start-up (v out1 =1.5v, v out2 = 1.05v, en2 = ref) figure 61. shutdown (v out1 =1.5v, v out2 = 1.05v, en2 = ref) figure 62. load transient v out1 =1.5v (pwm) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) en2 5v/div v out2 0.5v/div il2 2a/div pok2 2v/div en2 5v/div il2 2a/div pok2 2v/div v out2 0.5v/div en2 5v/div v out2 0.5v/div v out1 2v/div pok1 5v/div pok2 5v/div pok2 5v/div pok1 5v/div v out2 500mv/div v out1 2v/div en1 500mv/div en1 5v/div v out2 2v/div v out1 2v/div pok1 or pok2 5v/div lgate1 5v/div v out1 ripple 50mv/div il1 5a/div v out2 ripple 20mv/div isl6236 19 fn6373.6 april 29, 2010 typical application circuits the typical application circuits (figures 66, 67 and 68) generate the 5v/7a, 3.3v/11a, 1.25v/5a, dynamic voltage/10a, 1.5v/5a, 1.05v/5a and external 14v charge pump main supplies in a notebook computer. the isl6236 is also equipped with a secondary feedback, secfb, used to monitor the output of the 14v charge pump. in an event when the 14v drops below its threshold voltage, secfb comparator will turn on lgate1 for 300ns. this will refresh an external 14v charge pump without overcharging the ou tput voltage. the input supply range is 5.5v to 25v. detailed description the isl6236 dual-buck, bicmos, switch-mode power-supply controller generates logic supply voltages for notebook computers. the isl623 6 is designed primarily for battery-powered applications where high efficiency and low-quiescent supply current are critical. the isl6236 provides a pin-selectable switching frequency, allowing operation for 200khz/300khz, 400khz/300khz, or 400khz/500khz on the smpss. light-load efficiency is enha nced by automatic idle-mode operation, a variable-frequen cy pulse-skipping mode that reduces transition and gate-charge losses. each step-down, power-switching circuit consists of 2 n-channel mosfets, a rectifier, and an lc output filt er. the output voltage is the average ac voltage at the switching node, which is regulated by changing the duty cycle of the mosfet switches. the gate-drive signal to the n-channel high-side mosfet must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nf capacitor connected to boot. both smps1 and smps2 pwm controllers consist of a triple-mode feedback network and multiplexer, a multi-input pwm comparator, high-side and low-side gate drivers and figure 63. load transient v out1 = 1.5v (skip) figure 64. load transient v out1 = 1.05v (pwm) figure 65. load transient v out1 = 1.05v (skip) typical performance curves circuit of figures 66, 67 and 68, no load on ldo, out1, out2, v ref3 , and ref, v in = 12v, en2 = en1 = vcc, v byp = 5v, pvcc = 5v, v en ldo =5v, t a = -40c to +100c, unless otherwise noted. typical values are at t a = +25c. (continued) v out2 ripple 20mv/div il1 5a/div v out1 ripple 50mv/div lgate1 5v/div lgate2 5v/div v out1 ripple 20mv/div il1 5a/div v out2 ripple 20mv/div lgate2 5v/div v out1 ripple 20mv/div il2 5a/div v out2 ripple 20mv/div isl6236 20 fn6373.6 april 29, 2010 logic. in addition, smps2 can also use refin2 to track its output from 0.5v to 2. 50v. the isl6236 contains fault-protection circuits that monitor the main pwm outputs for undervoltage and overvoltage conditions. a power-on sequence block controls the pow er-up timing of the main pwms and monitors the outputs for undervoltage faults. the isl6236 includes an adjustable low drop-out linear regulator. the bias generator blocks incl ude the linear regulator, 3.3v precision reference, 2v prec ision reference and automatic bootstrap switchover circuit. the synchronous-switch gate drivers are directly powered from pvcc, while the high-side switch gate drivers are indirectly powered from pvcc through an external capacitor and an internal schottky diode boost circuit. an automatic bootstrap circuit turns off the ldo linear regulator and powers the device from byp if ldorefin is set to gnd or vcc. see table 1. free-running, constant on-time pwm controller with input feed-forward the constant on-time pwm control architecture is a pseudo-fixed-frequency, cons tant on-time, current-mode type with voltage feed-forward . the constant on-time pwm control architecture relies on the output ripple voltage to provide the pwm ramp signal; thus the output filter capacitor's esr acts as a current-feedback resistor. the high-side switch on-time is determined by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a minimum off-time (300ns typ). the on-time one-shot triggers when the following conditions are met: the error comparator's output is high, the synchronous rectifier current is below the current-limit threshold, and the minimum off time one-shot has timed out. the controller utilize the valley point of the output ripple to regulate and determine the off-time. on-time one-shot (t on ) each pwm core includes a one-shot that sets the high-side switch on-time for each controller. each fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. the high-side switch on-time is inversely proportional to the battery voltage as measured by the vin input and proportional to the output voltage. this algorithm results in a nearly constant switching fr equency despite the lack of a fixed-frequency clock generator. the benefit of a constant switching frequency is that the frequency can be selected to avoid noise-sensitive frequency regions: see table 2 for approximate k- factors. switching frequency increases as a function of lo ad current due to the increasing drop across the synchronous rectifier, which causes a faster inductor-current discharge ramp . on-times translate only roughly to switching frequencies. the on-times established in the ?electrical specifications? table starting on page 3 are influenced by switching delays in the external high-side power mosfet. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in pwm mode (skip = vcc) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the induct or's emf causes phase to go high earlier than normal, ext ending the on-time by a period equal to the ugate-rising dead time. for loads above the critical conduction point, the actual switching frequency is: where: ?v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances ?v drop2 is the sum of the parasi tic voltage drops in the charging path, including high-side switch, inductor, and pc board resistances ?t on is the on-time calculated by the isl6236 table 1. ldo output voltage table ldo voltage conditions comment voltage at byp ldorefin < 0.3v, byp > 4.63v internal ldo is disabled. voltage at byp ldorefin > vcc - 1v, byp > 3v internal ldo is disabled. 5v ldorefin < 0.3v, byp < 4.63v internal ldo is active. 3.3v ldorefin > vcc - 1v, byp < 3v internal ldo is active. 2 x ldorefin 0.35v < ldorefin < 2.25v internal ldo is active. table 2. approximate k-factor errors smps switching frequency (khz) k-factor (s) approximate k-factor error (%) (t on = gnd, ref, or open), v out1 400 2.5 10 (t on = gnd), v out2 500 2.0 10 (t on = vcc), v out1 200 5.0 10 (t on = vcc, ref, or open), v out2 300 3.3 10 t on kv out i load r ds on () lowerq () ? + () v in ---------------------------------------------------------------------------------------------------------- = (eq. 1) f v out v drop1 + t on v in v drop2 + () ------------------------------------------------------- = (eq. 2) isl6236 21 fn6373.6 april 29, 2010 ldo boot2 ugate2 phase2 lgate2 pgnd out2 refin2 en2 vin boot1 ugate1 phase1 lgate1 out1 agnd fb1 ilim1 skip en1 en ldo vin: 5.5v to 25v out2-gfx track refin2/10a out1 ? pci-e q1 irf7821 q2 irf7832 l2: 2.2h l1: 3.3h q3a si4816bdy q3b c1 10 c2 2 x 330f c4 0.22f r3 200k c10 10f c11 330f 6.3v vcc c5 isl6236 vcc 1.25v/5a c1 10f c2 4m 6.3v c9 c11 9m vcc ldorefin ton fb1 tied to gnd = 5v fb1 tied to vcc = 1.5v refin2 tied to vref3 = 1.05v refin2 tied to vcc = 3.3v pvcc c8 1f byp secfb refin2: dynamic 0 to 2.5v gnd 5v 2 bits dac 5v ilim2 vref3 pok1 r5 open vcc c3 r4 pok2 r6 vcc 200k 0.1f c7 ref pad r2 10k r1 7.87k nc gnd - + - + - + droop vcc + + 1f vcc 200k 200k frequency-dependent components 1.25v/1.05v smps switching frequency t on =vcc 200khz/300khz l1 3.3h l2 2.7h c2 2 x 330f c11 330f 0.1f figure 66. isl6236 typical dynamic gfx application circuit isl6236 22 fn6373.6 april 29, 2010 ldo boot2 ugate2 phase2 lgate2 pgnd out2 refin2 en2 vin boot1 ugate1 phase1 lgate1 out1 agnd fb1 ilim1 skip en1 en ldo vin: 5.5v to 25v out2 1.05v/5a out1 q1a l2: 2.2f l1: 3.3h q3a si4816bdy q3b c1 10 f ldo c2 330f c4 0.22f r3 200k c6 4.7f c10 10f c11 330f 6.3v vcc c5 isl6236 vcc 1.5v/5a c1 10 c2 4m 6.3v f c9 0.1f c11 9m on off on off off vcc ldorefin ton fb1 tied to gnd = 5v refin2 tied to vref3 = 1.05v refin2 tied to vcc = 3.3v pvcc c8 1f byp ldorefin tied to gnd = 5v ldorefin tied to vcc = 3.3v secfb refin2: dynamic 0v to 2.5v vcc 5v vcc 3.3v ilim2 vref3 pok1 r5 0.01f vcc c3 r4 pok2 r6 vcc 200k 200k 200k 0.1f c7 ref pad vcc si4816bdy vref3 vcc q1b fb1 tied to vcc = 1.5v frequency-dependent components 1.5v/1.05v smps switching frequency t on =vcc 200khz/300khz l1 3.3h l2 2.7h c2 330f c11 330f 1f figure 67. isl6236 typical system regulator application circuit without charge pump isl6236 23 fn6373.6 april 29, 2010 ldo boot2 ugate2 phase2 lgate2 pgnd out2 refin2 ilim2 vref3 pok1 en2 vin boot1 ugate1 phase1 lgate1 out1 agnd fb1 ilim1 skip en1 en ldo vin: 5.5v to 25v out2 3.3v/11a out1 q1 irf7821 q2 irf7832 l2: 4.7h l1: 4.7h q3 irf7807v q4 irf7811av c1 10 ldo c2 330f 9m c4 0.1f r3 r5 c6 4.7f open c9 c10 10f c11 330f 6.3v vcc c5 vcc isl6236 vcc 5v/7a c1 10f c2 4v c3 c9 9m r4 on off on off off vcc pok2 r6 vcc ldorefin ton fb1 tied to gnd = 5v fb1 tied to vcc = 1.5v refin2 tied to vref3 = 1.05v refin2 tied to vcc = 3.3v pvcc byp ldorefin tied to gnd = 5v ldorefin tied to vcc = 3.3v secfb refin2: dynamic 0 to 2v d1a d2 c8 0.1f c12 0.1f c14 0.1f c15 0.1f r1 200k r2 39.2k 200k 150k 200k 200k 0.1f c7 ref pad vcc cp 14v/10ma d1b d1 d2b d2a gnd d3 1f 0.1f frequency-dependent components 5v/3.3v smps switching frequency t on =vcc t on =ref (or open) t on =gnd 200khz/300khz 400khz/300khz 400khz/500khz l1 6.8h 6.8h 4.7h l2 7.6h 4.7h 4.7h c2 2x470f 2x330f 2x330f c11 330f 330f 330f figure 68. isl6236 typical system regulator application circuit with 14v charge pump isl6236 24 fn6373.6 april 29, 2010 i power-on squence clear fault latch smps1 synchronous pwm buck en1 pok1 en2 pok2 boot1 boot2 ugate2 lgate2 pgnd refin2 out2 pok1 ugate1 phase1 phase2 lgate1 fb1 out1 - + ldo vin en ldo en1 ton ilim2 vref3 thermal shutdown gnd power-on sequence clear fault latch ref vref3 pvcc - + - + ldo pvcc ilim1 thermal shutdown ldorefin pok2 sw threshold vcc 10 byp skip ref pvcc internal logic controller smps2 synchronous pwm buck controller en2 out2 out1 secfb figure 69. detailed functional diagram isl6236 isl6236 25 fn6373.6 april 29, 2010 automatic pulse-skipping switchover (idle mode) in idle mode (skip = gnd), an inherent aut omatic switchover to pfm takes place at light loads . this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero cros sing. this mechanism causes the threshold between pulse-skipping pfm and non-skipping pwm operation to coincide with the boundary between continuous and discontinuous in ductor-current operation (also known as the critical conduction point): where k is the on-time scale factor (see ?on-time one- shot (t on )? on page 20). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to half the peak-to-peak ripple current, which is a function of the inductor value (figure 71). for example, in the isl6236 typical application circuit with v out1 =5v, v in =12v, l = 7.6h, and k = 5s, switc hover to pulse-skipping operation occurs at i load = 0.96a or about on-fifth full load. the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. figure 71. ultrasonic current waveforms the switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a no rmal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs load curve, while higher values result in higher + skip + + + vin r s q q + + + a + s r q q + + + pgood fault latch to lgate driver ilim out + comp + + vin r s q r s q trig min. t off one shot q + + + s + + s r q s r q q + slope comp fb + + + + + 20ms to ugate driver out t on phase vcc 5a boot boot uv detect fb decoder vref one-shot 2v + secfb smsp1 only + refin2 (smps2) q ov latch uv latch fault latch logic blanking 0.9v ref 1.1v ref 0.7v ref figure 70. pwm controller (one side only) i load skip () kv out ? 2l ? ------------------------ v in v out ? v in ------------------------------- - = (eq. 3) on-time time i peak l v in -v out i t = inductor current i peak l v in -v t = 0 i peak l v in -v t = i peak v-v t = i load = i peak/2 isl6236 26 fn6373.6 april 29, 2010 full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). dc output accuracy specifications refer to the trip level of the error comparator. when the inductor is in continuous conduction, the output voltage has a dc regulation higher than the trip level by 50% of the ripple. in discontinuous conduction (skip = gnd, light load), the output voltage has a dc regulation higher than the tr ip level by approximately 1.0% due to slope compensation. forced-pwm mode the low-noise, forced-pwm (skip = vcc) mode disables the zero-crossing comparator, which controls the low-side switch on-time. disabling the zero-crossing detector causes the low-side, gate-drive waveform to become the complement of the high-side, gate-drive waveform. the inductor current reverses at light loads as the pwm loop strives to maintain a duty ratio of v out /v in . the benefit of forced-pwm mode is to keep th e switching frequency fairly constant, but it comes at a co st: the no-load ba ttery current can be 10ma to 50ma, depending on switching frequency and the external mosfets. forced-pwm mode is most useful for reducing audio-frequency noise, improvin g load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications t hat use a flyback transformer or coupled inductor. enhanced ultrasonic mode (25khz (min) pulse skipping) leaving skip unconnected or connecting skip to ref activates a unique pulse-skipping mode with a minimum switching frequency of 25khz. th is ultrasonic pulse-skipping mode eliminates audio-frequ ency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the controller automatically transi tions to fixed-frequency pwm operation when the load reaches the same critical conduction point (iload(skip)). an ultrasonic pulse occurs when the controller detects that no switching has occurred within the last 20s. once triggered, the ultrasonic controll er pulls lgate high, turning on the low-side mosfet to induce a negative inductor current. after fb drops below the regulation point, the controller turns off the low-side mosfet (lgate pulled low) and triggers a constant on-time (ugate driven high). when the on-time has expired, the controller re-enables the low-side mosfet until the cont roller detects that the inductor current dropped below the zero-crossing threshold. starting with a lgate pulse greatly reduces the peak output voltage when compared to starting with a ugate pulse, as long as vfb < vref, lgate is off and ugate is on, similar to pure skip mode. reference and linear regulators (vref3, ref, ldo and 14v charge pump) the 3.3v reference (vref3) is accurate to 1.5% over-temperature, making vref3 useful as a precision system reference. vref3 can supp ly up to 5ma for external loads. bypass vref3 to gnd with a 0.01f capacitor. leave it open if there is no load. the 2v reference (ref) is accu rate to 1% over-temperature, also making ref useful as a precision system reference. bypass ref to gnd with a 0.1f (min) capacitor. ref can supply up to 50a for external loads. an internal regulator produces a fixed 5v (ldorefin < 0.2v) or 3.3v (l dorefin > vcc - 1v). in an adjustable mode, the ldo output can be set from 0.7v to 4.5v. the ldo output voltage is equal to two times the ldorefin voltage. the ldo regulator can supply up to 100ma for external loads. bypass ldo with a minimum 4.7f ceramic capacitor. when the ldorefin < 0.2v and byp voltage is 5v, the ldo bootstrap-switchover to an internal 0.7 p-channel mosfet s witch connects byp to ldo pin while simultaneously shutting down the internal linear regulator. these actions bootstrap the device, powering the loads from the by p input voltages, rather than through internal linear regulators from the battery. similarly, when the byp = 3.3v and ldorefin = vcc, the ldo bootstrap-switchover to an internal 1.5 p-channel mosfet switch connects byp to ldo pin while simultaneously shutting down the internal linear regulator. no switchover action in adjustable mode. in figure 68, the external 14v charge pump is driven by lgate1. when lgate1 is low, d1a charged c8 sourced from out1. c8 voltage is equal to out1 minus a diode drop. when lgate1 transitions to high, the charges from c8 will transfer to c 12 through d1b and charge it to vlgate1 fb 28 fn6373.6 april 29, 2010 the internal pull-down transisto rs that drive lgate low have a 0.6 typical on-resistance. these low on-resistance pull-down transistors prevent lgate from being pulled up during the fast rise time of the inductor nodes due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfets. however, for high-current applications, some combinations of high- and low-side mosfets may cause excessive gate-drain coupling, which leads to poor efficiency and emi-producing shoot-through currents. adding a 1 resistor in series with boot increases the turn-on time of the high-side mosfets at the expense of efficiency, without degrading the turn-off time (figure 75). adaptive dead-time circuits monitor the lgate and ugate drivers and prevent either fet fr om turning on until the other is fully off. this algorithm allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be low resistance, low inductance paths from the gate drivers to the mosfet gates for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry interprets the mosfet gate as "off" when there is actually charge left on the gate. use very short, wide traces measuring 10 to 20 squares (50 mils to 100 mils wide if the mosfet is 1? from the device). boost-supply capacitor selection (buck) the boost capacitor should be 0.1f to 4.7f, depending on the input and output voltages, external components, and pc board layout. the boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low-side mosfet conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). the minimum gate to source voltage (v gs(min) ) is determined by: where: ? pvcc is 5v ?c gs is the gate capacitance of the high-side mosfet boost-supply refresh monitor in pure skip mode, the converter frequency can be very low with little to no output loading. this produces very long off times, where leakage can bleed down the boot capacitor voltage. if the voltage falls too low, the converter may not be able to turn on ugate when th e output voltage falls to the reference. to prevent this, the isl6236 monitors the boot capacitor voltage, and if it falls below 3v, it initiates an lgate pulse, which will refresh the boot voltage. por, uvlo and internal digital soft-start power-on reset (por) occu rs when vin rises above approximately 3v, resetting the undervoltage, overvoltage, and thermal-shutdown fault latches. pvcc undervoltage-lockout (uvlo) circuitry inhibits switching when pvcc is below 4v. lgate is low during uvlo. the output voltages begin to ramp up once pvcc exceeds its 4v uvlo and ref is in regulation. the internal digital soft-start timer begins to ramp up the maximum-allowed current limit during start-up. the 1.7ms ramp occurs in five steps. the step size are 20%, 40%, 60%, 80% and 100% of the positive current limit value. power-good output (pok) the pok comparator continuous ly monitors both output voltages for undervoltage conditions. pok is actively held low in shutdown, standby, and soft-start. pok1 releases and digital soft-start terminates when v out1 outputs reach the error-comparator threshold. pok1 goes low if v out1 output turns off or is 10% below its nominal regulation point. pok1 is a true open-drain output . likewise, pok2 is used to monitor v out2 . fault protection the isl6236 provides overvoltage/undervoltage fault protection in the buck controllers. once activated, the controller continuously monito rs the output for undervoltage and overvoltage fault conditions. out-of-bound condition when the output voltage is 5% above the set voltage, the out-of-bound condition activates. lgate turns on until output reaches within regulation. once the output is within regulation, the controller will oper ate as normal. it is the "first line of defense" before ovp. the output voltage ripple must be sized low enough as to not nuisance trip the oob threshold. the equations in ?o utput capacitor selection? on page 31 should be used to size the output voltage ripple below 3% of the nominal output voltage set point. 5v q1 vin out ugate c boot isl88732 isl88733 isl88734 10 boot out ugate phase isl6236 10 boot 5v 5v out ugate isl88732 isl88733 isl88734 10 boot out ugate isl6236 10 boot 5v 10 boot figure 75. reducing the switching-node rise time v gs min () pvcc c boot c boot c gs + --------------------------------------- ? = (eq. 5) isl6236 29 fn6373.6 april 29, 2010 overvoltage protection when the output voltage of v out1 is 11% (16% for v out2 ) above the set voltage, the overvoltage fault protection activates. this latches on the synchronous rectifier mosfet with 100% duty cycle, rapidl y discharging the output capacitor until the negative current limit is achieved. once negative current limit is met, ugate is turned on for a minimum on-time, followed by another lgate pulse until negative current limit. this effectively regulates the discharge current at the negative current limit in an effort to prevent excessively large negative currents that cause potentially damaging negative voltages on the load. once an overvoltage fault condition is set, it can only be reset by toggling shdn , en, or cycling vin (por). undervoltage protection when the output voltage drops below 70% of its regulation voltage for at least 100s, the controller sets the fault latch and begins the discharge mode (see ?shutdown mode? on page 29 and ?discharge mode (soft-stop)? on page 29). uvp is ignored for at least 20ms (typical), after start-up or after a rising edge on en. toggle en or cycle vin (por) to clear the undervoltage fault latch and restart the controller. uvp only applies to the buck outputs. thermal protection the isl6236 has thermal shutdown to protect the devices from overheating. thermal shutdown occurs when the die temperature exceeds +150c. all internal circuitry shuts down during thermal shutdown. the isl6236 may trigger thermal shutdown if ldo is not bootstrapped from out while applying a high input voltage on v in and drawing the maximum current (including short circuit) from ldo. even if ldo is bootstrapped from out, overloading the ldo causes large power dissipation on the bootstrap switches, which may result in thermal shutdown. cycling en, en ldo, or vin (por) ends the thermal-shutdown state. discharge mode (soft-stop) when a transition to standby or shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to gnd through an internal 25 switch. the reference remains active to provide an accurate threshold and to provide overvoltage protection. shutdown mode the isl6236 smps1, smps2 and ldo have independent enabling control. drive en1, en2 and en ldo below the precise input falling-edge trip level to place the isl6236 in its low-power shutdown state. the isl6236 consumes only 20a of quiescent current while in shutdown. when shutdown mode activates, the 3.3v vref3 remain on. both smps outputs are discharged to 0v through a 25 switch. power-up sequencing and on/off controls (en) en1 and en2 control smps power-up sequencing. en1 or en2 rising above 2.4v enables the respective outputs. en1 or en2 falling below 1.6v disables the respective outputs. connecting en1 or en2 to ref will force its outputs off while the other output is below r egulation. the sequenced smps will start once the other smps reaches regulation. the second smps remains on until the first smps turns off, the device shuts down, a fault occurs or pvcc goes into undervoltage lockout. both supplies begin their power-down sequence immediately when the first supply turns off. driving en below 0.8v clears the overvoltage, undervoltage and thermal fault latches. table 3. operating-mode truth table mode condition comment power-up pvcc < uvlo threshold. transiti ons to discharge mode after a vin po r and after ref becomes valid. ldo, vref3, and ref remain active. run en ldo = high, en1 or en2 enabled. normal operation overvoltage protection either output > 111% (vout1) or 116% (vout2) of nominal level. lgate is forced high. ldo, vref3 and re f active. exited by a vin por, or by toggling en1 or en2. undervoltage protection either output < 70% of nominal after 20ms time-out expires and output is enabled. the internal 25 switch turns on. ldo, vref3 and ref are active. exited by a vin por or by toggling en1 or en2. discharge either smps output is still high in either standby mode or shutdown mode discharge switch (25 ) connects out to gnd. one output may still run while the other is in discharge mode. activates when pvcc is in uvlo, or transition to uvlo, standby, or shutdown has begun. ldo, vref3 and ref active. standby en1, en2 < startup threshold, en ldo = high ldo, vref3 and ref active. shutdown en1, en2, en ldo = low discharge switch (25 ) connects out to pgnd. all circuitry off except vref3. thermal shutdown tj > +150c all circuitry off. exited by vin por or cycling en. vref3 remain active. isl6236 30 fn6373.6 april 29, 2010 adjustable-output feedback (dual-mode fb) connect fb1 to gnd to enable the fixed 5v or tie fb1 to vcc to set the fixed 1.5v output. connect a resistive voltage-divider at fb1 between out1 and gnd to adjust the respective output voltage between 0.7v and 5.5v (figure 76). choose r 2 to be approximately 10k and solve for r 1 using equation 6. where v fb1 = 0.7v nominal. likewise, connect refin2 to vcc to enable the fixed 3.3v or tie refin2 to vref3 to set the fixed 1.05v output. set refin2 from 0v to 2.50v for smps2 tracking mode (figure 77). where: ? vr = 2v nominal (if tied to ref) or ? vr = 3.3v nominal (if tied to vref3) design procedure establish the input voltage range and maximum load current before choosing an inductor and its associated ripple current ratio (lir). the following four factors dictate the rest of the design: 1. input voltage range. the maximum value (v in(max) ) must accommodate the maximum ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses and battery selector switches. lower input voltages result in better efficiency. 2. maximum load current. the peak load current (i load(max) ) determines the instantaneous component stress and filtering requirem ents and thus drives output capacitor selection, inductor saturation rating and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stress and drives the selection of input capa citors, mosfets and other critical heat-contributing components. 3. switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage and mosfet switching losses. 4. inductor ripple current ratio (lir). lir is the ratio of the peak-peak ripple current to the average inductor current. size and effici ency trade-offs must be considered when setting the inductor ripple current ratio. low inductor values cause lar ge ripple currents, resulting in the smallest size, but poor efficiency and high output noise. also, total output ri pple above 3.5% of the output regulation will cause the controller to trigger out-of-bound condition. the minimum practical inductor value is one that causes the circuit to operate at critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the isl6236 pulse-skipping algorithm (skip = gnd) initiates skip mode at the critical conduction point, so the inductor's operating point also determines the load current at which pwm/pfm switchover occurs. the optimum lir point is usually found between 25% and 50% ripple current. figure 76. setting v out1 with a resistor divider table 4. shutdown and standby control logis ven ldo ven1 (v) ven2 (v) ldo smps1 smps2 low low low off off off ?>2.5? high low low on off off ?>2.5? high high high on on on ?>2.5? high high low on on off ?>2.5? high low high on off on ?>2.5? high high ref on on on (after smps1 is up) ?>2.5? high ref high on on (after smps2 is up) on r 1 r 2 v out1 v fb1 ------------------ - 1 ? ?? ?? ?? ? = (eq. 6) r 3 r 4 vr v out2 ------------------ - 1 ? ?? ?? ? = (eq. 7) q3 v in out1 r1 r2 ugate1 lgate1 isl6236 out1 fb1 q4 isl6236 31 fn6373.6 april 29, 2010 inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as follows: example: i load(max) =5a, v in =12v, v out2 =5v, f = 200khz, 35% ripple current or lir = 0.35: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice. the core must be large enough not to saturate at the peak inductor current (ipeak): the inductor ripple current also impacts transient response performance, especially at low v in -v out differences. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the p eak amplitude of the output transient (vsag) is also a fu nction of the maximum duty factor, which can be calculated from the on-time and minimum off-time: where minimum off-time = 0.35s (max) and k is from table 2. determining the current limit the minimum current-limit th reshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the valley of the inductor current occurs at i load(max) minus half of the ripple current; therefore: where: i limit(low) = minimum current-l imit threshold voltage divided by the r ds(on) of q 2 /q 4 . use the worst-case maximum value for r ds(on) from the mosfet q 2 /q 4 data sheet and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.2% additional resistance for each c of temperature rise. examining the 5a circuit example with a maximum r ds(on) =5m at room temperature. at +125c reveals the following: 4.17a is greater than the vall ey current of 4.12a, so the circuit can easily deliver the full-rated 5a using the 30mv nominal current-limit threshold voltage. output capacitor selection the output filter capacitor must have low enough equivalent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. the output capacitance must also be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault latch. in applications where the output is subject to large load transients, the output capacitor's size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: where v dip is the maximum-tolerabl e transient voltage drop. in non-cpu applications, the output capacitor's size depends on how much esr is needed to maintain an acceptable level of output voltage ripple: where v p-p is the peak-to-peak output voltage ripple. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually q1 q2 v in ugate lgate isl88732 isl88733 isl88734 vout fb r3 r4 q2 out2 ugate2 lgate2 isl6236 out2 refin2 vr q2 ugate lgate isl88732 isl88733 isl88734 vout fb q2 ugate2 lgate2 isl6236 out2 refin2 vr figure 77. setting v out2 with a voltage divider for tracking l v out_ v in v out_ + () v in fliri load max () ?? ? --------------------------------------------------------------------- = (eq. 8) l 5v 12v 5v ? () 12v 200khz 0.35 5a ??? ----------------------------------------------------------------- 8.3 h == (eq. 9) ipeak i load max () lir 2 ? () i load max () ? [] + = (eq. 10) vsag i load max () () 2 lk v out_ v in ------------------ - t off min () + ?? ?? ?? ?? ?? ?? ? 2c out v out k v in v out ? v in ------------------------------- - ?? ?? ?? - t off min () ?? --------------------------------------------------------------------------------------------------------------------------- - = (eq. 11) i limit low () i load max () lir 2 ? () i load max () ? [] ? > (eq. 12) i limit low () 25mv () 5m 1.2 () 5a 0.35 2 ? () 5a ? > () ? = (eq. 13) 4.17a 4.12a > (eq. 14) r ser v dip i load max () --------------------------------- - (eq. 15) r esr v pp ? l ir i load max () ? ----------------------------------------------- (eq. 16) isl6236 32 fn6373.6 april 29, 2010 selected by esr and voltage rating rather than by capacitance value (this is true of tantalum, os-con, and other electrolytic-type capacitors). when using low-capacity filter capacitors such as polymer types, capacitor size is usually determined by the capacity required to prevent v sag and v soar from tripping the undervoltage and overvoltage fault latches during load transients in ultrasonic mode. for low input-to-output voltage differentials (v in /v out < 2), additional output capacitance is required to maintain stability and good efficiency in ultrasonic mode. the amount of overshoot due to stored inductor energy can be calculated as: where i peak is the peak inductor current. input capacitor selection the input capacitors must meet the input-ripple-current (i rms ) requirement imposed by the switching current. the isl6236 dual switching regu lator operates at different frequencies. this interleaves the current pulses drawn by the two switches and reduces the overlap time where they add together. the input rms current is much smaller in comparison than with both smpss operating in phase. the input rms current varies with load and the input voltage. the maximum input capacitor rms current for a single smps is given by: when , i rms has maximum current of . the esr of the input-capacitor is important for determining capacitor power dissipa tion. all the power (i rms 2 x esr) heats up the capacitor and reduces efficiency. nontantalum chemistries (ceramic or os-c on) are preferred due to their low esr and resilience to power-up surge currents. choose input capacitors that exhibi t less than +10c temperature rise at the rms input current for optimal circuit longevity. place the drains of the high-side switches close to each other to share common input bypass capacitors. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability (>5a) when using high-voltage (>20v) ac adapters. low-current applications usually require less attention. choose a high-side mosfet (q 1 /q 3 ) that has conduction losses equal to the switching losses at the typical battery voltage for maximum efficiency. ensure that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate the overall thermal budget. ensure that conduction losses plus switching losses at the maximum input voltage do not exceed the package ratings or violate the overall thermal budget. choose a synchronous rectifier (q 2 /q 4 ) with the lowest possible r ds(on) . ensure the gate is not pulled up by the high-side switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. switching losses are not an issue for the synchronous rectifier in the buck topology since it is a zero-voltage switched device when using the buck topology. mosfet power dissipation worst-case conduction losse s occur at the duty-factor extremes. for the high-side mosfet, the worst-case power dissipation (pd) due to the mosfet's r ds(on) occurs at the minimum battery voltage: generally, a small high-side mosfet reduces switching losses at high input voltage. however, the r ds(on) required to stay within package power-dissipation limits often limits how small the mosfet can be. the optimum situation occurs when the switching (ac) losses equal the conduction (r ds(on) ) losses. switching losses in the high-side mosfet can become an insidious heat problem when maximum battery voltage is applied, due to the squared term in the cv 2 f switching-loss equation. reconsider the high-side mosfet chosen for adequate r ds(on) at low battery voltages if it becomes extraordinarily hot when subjected to v in(max) . calculating the power dissipation in nh (q 1 /q 3 ) due to switching losses is difficult sinc e it must allow for quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for bench evaluation, preferably including verification using a thermocouple mounted on nh (q 1 /q 3 ): where c rss is the reverse transfer capacitance of q h (q 1 /q 3 ) and i gate is the peak gate-drive source/sink current. for the synchronous rectifier, the worst-case power dissipation always occurs at maximum battery voltage: v soar i peak 2 l ? 2c out v out_ ?? ----------------------------------------------- - = (eq. 17 ) i rms i load v out v in v out_ ? () v in ------------------------------------------------------------ ?? ?? ?? (eq. 18) v in 2v out_ d50% = () ? = i load 2 ? pd q h resistance () v out_ v in min () ------------------------ ?? ?? ?? i load () 2 r ds on () ? = (eq. 19 ) pd q h switching () v in max () () 2 c rss f sw i load ?? i gate ---------------------------------------------------- - ?? ?? ?? = (eq. 20 ) pd q l () 1 v out v in max () -------------------------- ? ?? ?? ?? i load 2 r ds on () ? = (eq. 21) isl6236 33 fn6373.6 april 29, 2010 the absolute worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the faul t latch to trip. to protect against this possibility, "overdesign" the circuit to tolerate: where i limit(high) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and resistance variation. rectifier selection current circulates from gr ound to the junction of both mosfets and the inductor when the high-side switch is off. as a consequence, the polarit y of the switching node is negative with respect to ground. this voltage is approximately -0.7v (a diode drop) at both transition edges while both switches are off (dead time). the drop is i l x r ds(on) when the low-side switch conducts. the rectifier is a clamp across the synchronous rectifier that catches the negative inductor swing during the dead time between turning the high-side mosfet off and the synchronous rectifier on. the mosfets incorporate a high-speed silicon body diode as an adequate clamp diode if efficiency is not of primary importance. place a schottky diode in parallel with the body diode to reduce the forward voltage drop and prevent the q2/q4 mosfet body diodes from turning on during the dead time. typically, the external diode improves the efficiency by 1% to 2%. use a schottky diode with a dc current rating equal to one-third of the load current. for example, use an mbr0530 (500ma-rated) type for loads up to 1.5a, a 1n5817 type for loads up to 3a, or a 1n5821 type for loads up to 10a. the rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. applications information dropout performance the output voltage-adjust range for continuous-conduction operation is restricted by the nonadjustable 350ns (max) minimum off-time one-shot. use the slower 5v smps for the higher of the two output voltages for best dropout performance in adjustable feedback mode. the duty-factor limit must be calculated using worst-case values for on - and off-times, when working with low input voltages. manufacturing tolerances and internal propagation delays introduce an error to the t on k-factor. also, keep in mind that transient-response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see equation 11 on page 31). the absolute point of dropout occurs when the inductor current ramps down during the minimum off-time ( i down ) as much as it ramps up during the on-time ( i up ). the ratio h = i up / i down indicates the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout po int, the inductor current is less able to increase duri ng each switching cycle and v sag greatly increases unless additional output capacitance is used. a reasonable minimum value for h is 1.5, but this can be adjusted up or down to allow trade-offs between v sag, output capacitance and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see ?on-time one-shot (t on )? on page 20), t off(min) is from th e ?electrical specifications? table, which starts on page 3 and k is taken from table 2. the absolute minimum input voltage is calculated with h = 1. operating frequency must be reduced or h must be increased and output capacitance added to obtain an acceptable v sag if calculated v in(min) is greater than the required minimum input voltage. calculate v sag to be sure of adequate transient response if operation near dropout is anticipated. dropout design example isl6236: with v out2 =5v, f sw = 400khz, k = 2.25s, t off(min) = 350ns, v drop1 =v drop2 = 100mv, and h = 1.5, the minimum v in is: calculating with h = 1 yields: therefore, v in must be greater than 6.65v. a practical input voltage with reasonable output capacitance would be 7.5v. pc board layout guidelines careful pc board layout is critical to achieve minimal switching losses and clean, stable operation. this is especially true when multiple converters are on the same pc board where one circuit can affect the other. re fer to the isl6236 evaluation kit application notes (an1271 and an1272) for a specific layout example. i load i limit high () lir () 2 ? () i load max () ? + = (eq. 22) v in min () v out_ v drop + () 1 t off min () h ? k ----------------------------------- - ?? ?? ? -------------------------------------------------- - v drop2 v drop1 ? + = (eq. 23) v in min () 5v 0.1v + () 1 0.35 s1.5 ? 2.25 s ------------------------------- ?? ?? ? ---------------------------------------------- 0.1v 0.1v 6.65v = ? + = (eq. 24) v in min () 5v 0.1v + () 1 0.35 s1 ? 2.25 s -------------------------- ?? ?? ? ----------------------------------------- 0.1v 0.1v 6.04v = ? + = (eq. 25) isl6236 34 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6373.6 april 29, 2010 mount all of the power components on the top side of the board with their ground terminals flush against one another, if possible. follow these guidelines for good pc board layout: ? isolate the power components on the top side from the sensitive analog components on the bottom side with a ground shield. use a separate pgnd plane under the out1 and out2 sides (called pgnd1 and pgnd2). avoid the introduction of ac currents into the pgnd1 and pgnd2 ground planes. run the power plane ground currents on the top side only, if possible. ? use a star ground connection on the power plane to minimize the crosstalk between out1 and out2. ? keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. ? keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces must be approached in terms of fracti ons of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. ? phase (isl6236) and gnd connections to the synchronous rectifiers for cu rrent limiting must be made using kelvin-sense connect ions to guarantee the current-limit accuracy with 8 ld so mosfets. this is best done by routing power to the mosfets from outside using the top copper layer, while connecting phase traces inside (underneath) the mosfets. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the synchronous rectifier or between the inductor and the output filter capacitor. ? ensure that the out connection to cout is short and direct. however, in some ca ses it may be desirable to deliberately introduce some trace length between the out connector node and the output filter capacitor. ? route high-speed switchin g nodes (boot, ugate, phase, and lgate) away from sensitive analog areas (ref, ilim, and fb). use pgnd1 and pgnd2 as an emi shield to keep radiated switching noise away from the ic's feedback divider and analog bypass capacitors. ? make all pin-strap control input connections (skip , ilim, etc.) to gnd or vcc of the device. layout procedure place the power components first with ground terminals adjacent (q 2 /q 4 source, c in , c out ). if possible, make all these connections on the top layer with wide, copper-filled areas. mount the controller ic adjacent to the synchronous rectifier mosfets close to the hottest spot, preferably on the back side in order to keep ugate, gnd, and the lgate gate drive lines short and wide. the lgate gate trace must be short and wide, measuring 50 mils to 100 mils wide if the mosfet is 1? from the controller device. group the gate-drive compone nts (boot capacitor, vin bypass capacitor) together near the controller device. make the dc/dc controller ground connections as follows: 1. near the device, create a small analog ground plane. 2. connect the small analog ground plane to gnd and use the plane for the ground connection for the ref and vcc bypass capacitors, fb dividers and ilim resistors (if any). 3. create another small ground island for pgnd and use the plane for the vin bypass capacitor, placed very close to the device. 4. connect the gnd and pgnd planes together at the metal tab under device. on the board's top side (power planes), make a star ground to minimize crosstalk between the two sides. the top-side star ground is a star connection of the input capacitors and synchronous rectifiers. keep the resistance low between the star ground and the source of the synchronous rectifiers for accurate current limit. connect the top-side star ground (used for mosfet, input, and output capacitors) to the small island with a single short, wide connection (preferably just a via). create pgnd islands on the layer just below the topside layer (refer to the isl6236 evaluation kit application notes, an1271 and an1272) to act as an emi shield if multiple layers are available (highly recommended). connect each of these individually to the star ground via, which connects the top side to th e pgnd plane. add one more solid ground plane under the device to act as an additional shield, and also connect the solid ground plane to the star ground via. connect the output power planes (vcore and system ground planes) directly to the ou tput filter capa citor positive and negative terminals with multiple vias. isl6236 35 fn6373.6 april 29, 2010 isl6236 package outline drawing l32.5x5b 32 lead quad flat no-lead plastic package rev 2, 11/07 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 5.00 a 5.00 b index area pin 1 6 (4x) 0.15 32x 0.40 0.10 4 a 32x 0.23 m 0.10 c b 16 9 4x 0.50 28x 3.5 6 pin #1 index area 3 .30 0 . 15 0 . 90 0.1 base plane see detail "x" seating plane 0.10 c c 0.08 c 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 30 ) ( 4. 80 typ ) ( 28x 0 . 5 ) (32x 0 . 23 ) ( 32x 0 . 60) + 0.07 - 0.05 17 25 24 8 1 32 |
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